This paper presents Design of NIOS II Based
Embedded web server for networking applications. The
ALTERA’s SOPC (System on Programmable chip)
Development tool is used to implement the system, which
contains NIOS II Core Processor. It includes development of
Embedded WEB Server application design based on the
µCLINUX Kernel. The Hardware Device is based on FPGA
and describe through VHDL. We have used CYCLONE II
family of FPGA EP2C20C484C7 to base the prototype and
NIOS II soft-core processor to run application algorithm.
Published In : IJCSN Journal Volume 3, Issue 3
Date of Publication : 01 June 2014
Pages : 12 - 16
Figures : 10
Tables : --
Publication Link : NIOS II Based Embedded Web Server Development
for Networking Applications
Ms. Sheetal Bhoyar : Research Scholar, G. H. Raisoni College of Engineering, Nagpur, India
Dr. D. V. Padole
: Professor, G. H. Raisoni College of Engineering, Nagpur, India
This paper presented the development of WEB Server
based on µCLINUX KERNEL in the NIOS II Core
processors of ALTERA Cyclone II family FPGA board.
The NIOS II using proved be suitable and simple to use,
but requires the license. Recent development of soft-core
processors on Field Programmable Gate Arrays(FPGAs)
provide customization of processor to the needs of target
application over traditional pre-fabricated processors.
Soft-core processors are available in the form of
software whose architecture and behavior are fully
described by pre-designed and pre-tested Intellectual
Properties (IP's), these can be synthesized on FPGAs. It
provide several advantages such as reduced cost,
reduction in components, flexibility in choosing specific
peripheral etc.
[1] QUARTUS II Software information and download.
http://www.altera.com/products/software/quartusII
[2] Tutorials for NIOSII implementation:
http://www.doulos.com/content/training/altera_niosII_tr
aining.php.
[3] ALTERA Documentation: NIOS Processor, Available
online:http://www.altera.com/literature/ds lit-nio.jsp,
June 2012
[4] Application Research of NIOS II Technology on
Logging Device of Ground:
http://ieeexplore.ieee.org/xpl/freeabs_all.jsp
[5] Hardware-Accelerated NIOS-II Implementation of a
Turbo Decoder:
http://ieeexplore.ieee.org/xpl/freeabs_all.jsp
[6] ALTERA, Corp, 2009. Avalon Bus Specification
Reference Manual.
http://www.altera.com/literature/manual/mnl-avalonspec.
pdf.
[7] ALTERA, Corp, 2009. SOPC Builder Support,
http://www.altera.com/support/software/system/sopc/sof
sopc_builder.html. Accessed.
[8] Petar Borisov Minev (Technical University of Gabrovo)
and Valentina Stoianova Kukenska (Technical
University of Gabrovo) “Implementation Of Soft-Core
Processors In Fpgas”, In “International Scientific
Conference” 23 – 24 November 2007.
[9] Stephen MacMahon, Nan Zang, Anirudha Sarangi
“LightWeight IP (lwIP) Application Examples”, XAPP
1026 (V3.1) , April 21, 2011
[10] Fang Yi-yuan; Chen Xue-jun; , "Design and Simulation
of UART Serial Communication Module Based on
VHDL,"
Intelligent Systems and Applications (ISA), 2011 3rd
International Workshop on , vol., no., pp.1-4, 28-29 May
2011.
