RC4 Stream cipher is well known for its simplicity and ease to develope in software. But here, in the proposed design we have heighlighted the modified hardware implémentation of RC4. As RC4 is the most popular stream cipher. The proposed design performs reading and swapping simultaneously in one clock cycle. The proposed design also highlights the adder part which enhances the architecture speed. As this design uses fast Carry Look Ahead Adder as the adder logic. In this paper we have compared the proposed design with the other existing design which also works on one byte per clock cycle [1].

 

Published In : IJCSN Journal Volume 3, Issue 6

Date of Publication : December 2014

Pages : 470 - 471

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Tables : 01

Publication Link : Comparison of Compact High Speed Reconfigurable RC4 Hardware with the Existing RC4 Hardware

 

 

 

Priya Nagar : is working as Lecturer in Electronics Department at G.H.Raisoni Institute of Engineering and Technology Pune. She is pursuing her M.E in VLSI & Embedded Systems.

 

 

 

 

 

 

 

CLA

Clock

FPGA

RC4

Throughput

In this paper hardware implementation of RC4 performing swapping and reading simultaneously in one clock cycle is compared with the existing hardware [1] One byte per clock cycle. The comparisons based in terms of number of components used, type of adder, methods of computation and number of clock cycle. The proposed design uses fewer components, which is major advantage of this system. These ciphers were coded in VHDL language and synthesized in an FPGA device.

 

 

 

 

 

 

 

 

 

[1] Andrew S. Tanenbaum, “Computer Networks”, Fourth edition, Peaeson Education , 2005. pp. 292-302. [2] Douglas A. Pucknell, Kamran Eshraghian, “Basic VLSI design”, 3rd Edition, Prentice Hall of India, 2004. pp. 118-274. [3] Stephen Brown Zvonk Vransic, “Fundamentals of Digital Logic Design with VHDL”, Second editation, Tata Mcgraw Hill, 2005. pp. 315-724. [4] Sourav Sen Gupta1, Koushik Sinha2, Subhamoy Maitra1, and Bhabani P. Sinha,” One Byte per Clock: A Novel RC4 Hardware”, ndian Statistical Institute, 203 B T Road, Kolkata 700 108, India 2 Honeywell Technology Solutions Lab, Bangalore 560 076, India. [5] P.kitsos, G. Kostopoulos, N. Sklavos and O.Koufopavlou, “Hardware implementation of the RC4 stream cipher ”, IEEE Std 802.11. IEEE Standard. [6] Yu-Ting Pai And Yu-Kumg Chen,” The Fastest Carry Lookahead Adder”