Continuous scaling of CMOS expertise makes the
integration of large number of heterogeneous devices which
results in efficient communication on a single chip. This is the
purpose for which competent routers are desirable as a result
of which communication takes place between these devices.
The proposed methodology gives the method for on-chip
routers based on combination of the XY and (Virtual cut
through) VCT router for better and optimized data transfer.
In this paper the proposed design of on-chip router give the
outcome as the optimized routing output because of the
priority allocate to the input data packet. The dynamic
arbitration technique using VCT and XY is explained in this
paper.
Bharati B. Sayankar : Electronics Department, Rashtrasant Tukdoji Maharaj Nagpur University, G.H. Raisoni College Of Engineering,
Nagpur, Maharashtra, India
Pankaj Agrawal : Electronics Department, Rashtrasant Tukdoji Maharaj Nagpur University, G.H. Raisoni Academy of Engineering & Technology,
Nagpur, Maharashtra, India
Arbiter
Network on chip (NOC)
On chip Router
XY Router
Virtual out through (VCT) router
Cross Bar Switch
Table 1 shows the comparative results of the XY router,
and VCT router. As shown in table 1, utilization of
number of slices, number of slices flip flop and number of
4 input LuTs in XY is better than VCT. Hence from the
above result we can say that XY router results are better
than VCT router. The utilization of same parameters is
further improved when the combination of XY and VCT
router is used. Path selection can be done based on XY
routing. We would be selecting a Virtual Channel to pass
packets, thus the system would be having advantages of
the VCT algorithm. “The authors declare that they have no
competing interests.”
[1] V.Soteriou, R.S. Ramanujam, B. Lin, Li-Shiuan Peh. A
High- Throughput Distributed Shared-Buffer NoC
Router. IEEE Computer Architecture Letters, vol. 8,
no. 1, pp. 21-24, Jan.-June 2009, doi:10.1109/LCA.
2009.5. [2] A. Louri, J. Wang, Design of energy-efficient channel
buffers with router bypassing for network-on-chips
(NoCs).”
[3] H. C. Freitas and C. A. P. S. Martins, “Didactic
Architectures and Simulator for Network Processor
Learning”, Workshop on Computer Architecture
Education, San Diego, CA, USA, 2003, pp.86-95
[4] A. Kodi, A. Louri, J. Wang. Design of energyefficientnchannel
buffers with router bypassing for
network-onchips (NoCs). Proceedings of International
Symposium on Quality of Electronic Design (ISQED),
pp.826-832, March 2009.
[5] Khalid Latif, Moazzam Niazi, Hannu Tenhunen,
Tiberiu Seceleanu, Sakir Sezer. Application
development flow for on-chip distributed architectures.
Proceedings of IEEE International SoC Conference
(SOCC), Sept. 2008, pp. 163-168.