Generation of a High Resolution Pulse Width Modulated Wave Using FPGA

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This paper proposes a new digital pulse width modulation (DPWM) architecture that takes advantage of the field programmable gate array’s (FPGA)advanced characteristics, especially the delay-locked loop (DLLs) present in almost every FPGA. The proposed DPWM combines a synchronous (counter based) block with an asynchronous block for increased resolution without unnecessarily increasing the clock frequency. The experimental results show an implementation in a low-cost FPGA (Xilinx Spartan-3) that uses an external 32 MHz clock for a final time resolution.

Published In : IJCSN Journal Volume 5, Issue 5

Date of Publication : October 2016

Pages : 741-745

Figures :07

Tables : 01

Kishore Ramesh Badgujar : Yadavrao Tasgaonkar College Of Engineering & Management, University of Mumbai, Bhivpuri, Karjat, India.

Pankaj A. Salunkhe : Yadavrao Tasgaonkar College Of Engineering & Management, University of Mumbai, Bhivpuri, Karjat, India.

Tushar M. Patil : G.H.Raisoni Institute of Engg. & Management North Maharashtra university, Jalgaon, India.

Digital Control, Field Programmable Gate Array, Pulse Width Modulator, Signal Resolution

A new hybrid counter-asynchronous DPWM architecture has been proposed. This DPWM , which is easy to design is mainly intended for FPGA implementation. The DLL raises the resolution of the DPWM. The external clock frequencies internally multiplied for a higher resolution. Once the maximum possible resolution is achieved in the synchronous block, it is multiplied by 4 using four phaseshifted clock outputs of the DLL. The proposed DPWM has been verified through experimental results using a lowcost FPGA implementation (Spartan-3), which shows the feasibility of the method not only for prototyping purposes but also for final products.

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