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  Implementation of Fast Fourier Transform Accelerator on Coarse Grain Reconfigurable Architecture  
  Authors : Vaishali Tehre; Dr. Pankaj Agrawal; Dr. R.V. Kshrisagar
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Recent technology growth permit engineer to design various complex applications on single-on-chip (SoC) related to communication, Image Processing, video processing, digital signal processing. In all of these complex algorithms, FFT blocks are one of the most computation concentrated. Here we first introduce a novel Coarse-Grain Reconfigurable Array (CGRA) which is used as a hardware accelerator to optimize the performance of system. The architecture consist of processing elements (PEs), configuration controller and interconnection network on a single chip. Subsequently we present a mapping of different length of Fast Fourier Transform (FFT) algorithms on them. In this paper, we have considered radix-(2, 4) FFT accelerators which are mapped on 4X4 PE CGRA templates. We estimated their power and energy consumption. A Field Programmable Gate Array (FPGA) is used to implement prototype of CGRA. Based on the measurements, we have compared results with other implementations.

 

Published In : IJCSN Journal Volume 5, Issue 6

Date of Publication : December 2016

Pages : 955-959

Figures :05

Tables : 02

 

Vaishali Tehre : Electronics Department, G .H. Raisoni college of Engineering Nagpur University Nagpur, Maharashtra, India.

Dr. Pankaj Agrawal : Department of Electronics, G.H. Raisoni Academy of Engineering and Technology Nagpur, India, Nagpur, Maharashtra, India.

Dr. R.V. Kshrisagar : Priyadarshini Indira Gandhi College of Engineering Nagpur, Maharashtra, India.

 

 

 

 

 

 

 

Coarse Grain Reconfigurable Architecture (CGRA), Low Power, FPGA, ASIC, Processing Element

In this paper, we have presented the design of a large scale template based Coarse Grain Reconfigurable Array on which various algorithm can be mapped. An 8 point Fast Fourier Transform kernels were mapped on it. The simulation and synthesis results show the performance of the Fast Fourier Transform accelerators. Table 2 lists the power consumption (dynamic power PDyn and total core power PCore) and energy efficiency (EEff) performance for benchmark applications. All figures are generated at 100 MHz. Frequency. The processing units consume about 51% of total power, with 33% for ALUs and 8% for logic components. The on-chip memories and interconnections consume another 53% of total power. The propose CGRA consumes less power as compared to conventional FPGA when the intensive application mapped on it.

 

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