Security and confidentiality are the prime factors in the field of Cyber security based applications. The Lightweight cryptography gives a solution tailored for the efficient VLSI implementations of resource-constrained devices. A high performance design for the PRESENT block cipher has been proposed. The designed architecture carry out the encryption operation by using key of 80 bit length and an input data of 64 bit. The simulation is carried through Xilinx ISE 14.7 design suite using verilog code and synthesized for Spartan-6 XC65LX45 FPGA device. The performance metrics like throughput, area and power are measured based on the synthesis report. The PRESENT block cipher consumes only 90 slices on total, hence the area consumed is around 0.75% and power consumed is about 36.61mW.
The PRESENT Lightweight cipher has been designed using verilog code and is synthesized through Xilinx ISE Design suite with the key length of 80 bit. Then the design is implemented trough Spartan-6 XC6SLX45 FPGA kit and the output is analyzed through the chip scope. Finally based on the synthesis report performance parameters are measured. When compared to other existing implementations, the proposed architecture performs better and provides high throughput. Further the design can be implemented with 128-bit key for the same input data for and analyse the performance and make use of different kit versions.
[1] Jai Gopal Pandey, Tarun Goel, Abhijit Karmakar, "A High-performance and Area-efficient VLSI Architecture for the PRESENT Lightweight Cipher", International Conference on Embedded Systems, January 2018.
[2] William J. Buchanan, Shancang Li & Rameez Asif, "Lightweight cryptography methods", Journal of Cyber Security Technology, VOL. 1, NOS. 3-4, pp. 187-201, 2017.
[3] Chao Pei, Yang Xiao, Wei Liang, Xiaojia Han, "Trade-off of security and performance of lightweight block ciphers in Industrial Wireless Sensor Networks," EURASIP Journal on Wireless Communications and Networking, May 2018.
[4] C.A. Lara-Nino, M. Morales-Sandoval, and A. Diaz-Perez, "Novel FPGA-based low-cost hardware architecture for the PRESENT block cipher", in 2016 Euromicro Conference on Digital System Design, 2016. [5] A. Bogdanov, L.R. Knudsen, G. Leander, C. Paar, A. Poschmann, M.J.B. Robshaw, Y. Seurin, and C. Vikkelsoe, "PRESENT: An Ultra-Lightweight Block Cipher", Cryptographic Hardware and Embedded Systems (CHES), Lecture Notes in Computer Science, pp. 450-466,2007.
[6] Sufyan Salim Mahmood AlDabbagh, Imad Fakhri Taha Al Shaikhli, "Improving PRESENT Lightweight Algorithm", International Conference on Advanced Computer Science Applications and Technologies, pp. 4799-2758,2013.
[7] Z. Ma, A. Hudic, A. Shaaban and S. Plosz, "Security Viewpoint in a Reference Architecture Model for
Cyber-Physical Production Systems", 2017 IEEE European Symposium on Security and Privacy Workshops (EuroS&PW),Paris,2017,pp.153-159.
[8] Tadashi Okabe, "FPGA Implementation and Evaluation of lightweight block cipher - BORON", International Journal of Engineering Development and Research, Volume 5, Issue 1,2017.
[9] Hatzivasilis, George, Konstantinos Fysarakis, Ioannis Papaefstathiou, and Charalampos Manifavas. "A review of lightweight block ciphers." Journal of Cryptographic Engineering 8, no. 2 (2018): 141-184.
[10] Elif Bilge Kavun, Tolga Yalcin, "RAM-Based Ultra-Lightweight FPGA Implementation of PRESENT", International Conference on Reconfigurable Computing and FPGAs, pp. 2325-6532, Dec. 2011. [11] Anjan K, Abhijith C, Arunraj, Deekshith N, Design and Mathematical Model of Hybrid Cryptographic Algorithm- A3D Algorithm, IJARCCE, Vol 3, Issue 6, Jun 2014.
[12] Bharathi R , N. Parvatham , "LEA-SIoT: Hardware Architecture of Lightweight Encryption Algorithm for Secure IoT on FPGA Platform", (IJACSA) International Journal of Advanced Computer Science and Applications, Vol. 11, Issue 1, January 2020.
