Security and confidentiality are the prime factors in the field of Cyber security based applications. The Lightweight cryptography gives a solution tailored for the efficient VLSI implementations of resource-constrained devices. A high performance design for the PRESENT block cipher has been proposed. The designed architecture carry out the encryption operation by using key of 80 bit length and an input data of 64 bit. The simulation is carried through Xilinx ISE 14.7 design suite using verilog code and synthesized for Spartan-6 XC65LX45 FPGA device. The performance metrics like throughput, area and power are measured based on the synthesis report. The PRESENT block cipher consumes only 90 slices on total, hence the area consumed is around 0.75% and power consumed is about 36.61mW.
The PRESENT Lightweight cipher has been designed using verilog code and is synthesized through Xilinx ISE Design suite with the key length of 80 bit. Then the design is implemented trough Spartan-6 XC6SLX45 FPGA kit and the output is analyzed through the chip scope. Finally based on the synthesis report performance parameters are measured. When compared to other existing implementations, the proposed architecture performs better and provides high throughput. Further the design can be implemented with 128-bit key for the same input data for and analyse the performance and make use of different kit versions.
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